The present invention generally relates to digital logic families, and more particularly, to digital logic families for high speed circuits.
Moore's Law, which is named after the founder of Intel Corporation, Gordon Moore, states that the speed and density of computers will double every 18-24 months. For the most part, Moore's Law has held true since the early days of the microprocessor, and is predicted to do so for at least another twenty years.
A corollary to Moore's Law is that the size of the transistors used in integrated circuits must shrink by a factor of two every 18-24 months. Until recently, this was accomplished by simply scaling bulk MOSFET devices. However, as the transistor channel lengths scale below about 0.25 um, a number of transistor effects begin to degrade the transistor's characteristics. Some of these effects include short-channel effects, gate resistance effects, channel profiling effects and other effects. It has been found that reducing the power supply voltage can reduce some of these effects, but the performance of the resulting circuit also tends to suffer.
A number of logic families have been proposed for producing higher performance circuits, some of which use pass-transistor logic. Pass-transistor logic families often can implement a desired logic function using fewer transistors than conventional CMOS logic. One common pass-transistor logic family is known as Complementary Pass-transistor Logic (CPL), and is discussed in U.S. Pat. No. 5,808,483 to Sako and in "A 1.5-ns 32-b CMOS ALU in Double Pass-Transistor Logic" by Suzuki et al. A typical CPL logic gate uses only NMOS transistors to produce relatively low input capacitances and relatively high performance circuits.
A limitation of many pass-transistor logic families, including CPL is that the high output signal level tends to be lower than the supply voltage by an NMOS threshold voltage. This reduces the noise margin of the circuit, and in turn, the speed of the circuit. The usual way to avoid this is to use CMOS Pass-Transistor Logic, where full-swing operation is achieved by adding PMOS transistors in parallel with the NMOS transistors of a CPL gate. This, however, produces higher input capacitance and slower circuit performance.
Another pass-transistor logic family is called Dual Pass-Transistor Logic (DPL). Dual Pass-Transistor Logic (DPL) is a modified version of CPL, and is often used for reduced supply voltage applications. Unlike CPL, DPL uses both NMOS and PMOS pass-transistors. A typical DPL AND/NAND gate is shown in FIG. 1, with the NAND gate shown at 100 and the AND gate shown at 102. Both the NAND gate 100 and the AND gate 102 use complementary input signals A, A, B and B.
For the NAND gate 100, input A is coupled to the gate terminals of NMOS transistor 104 and PMOS transistor 106. PMOS transistor 106 has a source that is coupled to a power supply voltage (VDD) 107, and a drain that is coupled to an output terminal 112. NMOS transistor 104 has a source that is coupled to the input B, and a drain that is coupled to the output terminal 112.
Input B is coupled to the gate terminals of NMOS transistor 108 and PMOS transistor 110. PMOS transistor 110 has a source that is coupled to the power supply voltage (VDD) 107, and a drain that is coupled to the output terminal 112. NMOS transistor 108 has a source that is coupled to input A, and a drain that is coupled to the output terminal 112.
For the AND gate 102, input A is coupled to the gate terminals of NMOS transistor 120 and PMOS transistor 122. NMOS transistor 120 has a source that is coupled to ground 123, and a drain that is coupled to output terminal 124. PMOS transistor 122 has a source that is coupled to the input B, and a drain that is coupled to the output terminal 124.
Input B is coupled to the gate terminals of NMOS transistor 126 and PMOS transistor 128. NMOS transistor 126 has a source that is coupled to ground 123, and a drain that is coupled to the output terminal 124. PMOS transistor 128 has a source that is coupled to input A, and a drain that is coupled to the output terminal 124.
Dual Pass-Transistor Logic (DPL) can produce higher circuit performance than CPL because dual current paths are available for driving the output of the gate. For example, for the NAND gate 100 shown in FIG. 1, when inputs A and B are both low, PMOS transistor 106 and PMOS transistor 110 are both "on". Thus, PMOS transistor 106 provides a first current path for pulling the output terminal 112 high, and PMOS transistor 110 provides a second current path for pulling the output terminal 112 high.
When input A is low and input B is high, PMOS transistor 106 is "on", and NMOS transistor 108 is "on" with the drain pulled high (i.e., input A is high). Accordingly, PMOS transistor 106 provides a first current path for pulling output 112 high, and NMOS transistor 108 provides a second current path for pulling the output terminal 112 high.
When input A is high and input B is low, PMOS transistor 110 is "on", and NMOS transistor 104 is "on" with the drain pulled high (i.e., input B is high). Accordingly, PMOS transistor 110 provides a first current path for pulling output terminal 112 high, and NMOS transistor 104 provides a second current path for pulling output terminal 112 high.
Finally, when input A and input B are both high, NMOS transistor 104 is "on" and NMOS transistor 108 is "on", both with their drains pulled low (i.e., both A and B are low). As such, NMOS transistor 104 provides a first current path for pulling the output terminal 112 low, and NMOS transistor 108 provides a second current path for pulling the output terminal 112 low.
The dual current paths provided by DPL are thought to increase the performance of DPL relative to CPL. In addition, the dual current paths are thought to allow rail-to-rail switching, which may increase the noise margin and performance of DPL relative to CPL, especially under reduced power supply conditions.